The subject application is related to subject matter disclosed in the Japanese Patent Application No.Hei11-269484 filed in Sep. 22, 1999 in Japan, to which the subject application claims priority under the Paris Convention and which is incorporated by reference herein.
1. Field of the Invention
The present invention relates to a standard cell and a semiconductor integrated circuit attained by a combination of the standard cells.
2. Description of the Related Art
Associated with a growth of a large scale of a semiconductor integrated circuit, it becomes difficult to completely design by only a man power. For this reason, a semi-custom design method for an automatic design through a computer has been typically used. This semi-custom design method is a method for preparing a plurality of standard basic circuits (logical cells) in advance, automatically designing those logical cells by using the computer, and then developing a desirable circuit. As a typical example of the method, there are a gate array method and a standard cell method.
In the standard cell method, a slightly complex logic circuit generated by a combination of basic circuits is optimally designed in advance, and stored as a cell in a database of the computer. When LSI is actually designed, the desirable circuit is attained by a combination of various cells stored in the database. The respective cells are constant in height, and the necessary cells are arranged in a plurality of rows. The database for storing the cells is referred to as a cell library. As kinds of cells stored in this cell library are richer, it is possible to design an LSI chip with smaller waste.
In recent years, a cell base ASIC in which a standard cell and a macro cell (block) of a high function can be mixed has been used as a main method for semi-custom design. Especially, a cell base ASIC using a standard cell is developed in which a cell region (transistor region) and a wiring cannel region are mixed. The expectation is growing for its high integration degree.
On the other hand, associated with increase in an integration density of the semiconductor integrated circuit, the miniaturization of a cell size has been required more and more. Typically, if a transistor size is reduced in each cell, it is possible to reduce the cell size. However, the equal reduction in the transistor size causes a drive performance of the cell to be dropped. In the standard cell method, the respective cells are arranged in a plurality of rows. So, there may be a case of a circuit configuration sharable between cells adjacent to each other. Thus, if the circuit configuration is collected into one, the cell row can be reduced to thereby reduce the apparent cell size. As a conventionally used method, there is a method in which a substrate contact region for applying a potential to a substrate (in a case of a well structure, the well) is mounted at a center of cells adjacent to each other in an upper and lower direction, and then the substrate contact region is shared between the cells. However, in this method, even if the cell row can be reduced in the upper and lower direction, it is naturally impossible to reduce in a left and right direction. Hence, it is desirable to attain a method for reducing the cell row even in the left and right direction and effectively reduce the cell size.
The present invention is proposed in view of the above mentioned circumstances. It is therefore an object of the present invention to reduce an effective cell size both in an upper and lower direction and in a left and right direction and thereby provide a standard cell for improving an integration density of a semiconductor integrated circuit.
Another object of the present invention is to provide a semiconductor integrated circuit which can be attained by a combination of the above-mentioned standard cells and highly integrated.
Still another object of the present invention is to provide a method for designing a semiconductor integrated circuit, which can be attained by the combination of the above-mentioned standard cells and highly integrated.
In order to solve the above-mentioned problems, the feature of the present invention lies in a standard cell having a plurality of MOS transistors formed on a semiconductor substrate, in which the standard cells are adjacent to each other in upper, lower, left and right directions and constitute a semiconductor integrated circuit, the standard cell further comprising: (a) a boundary line between cells adjacent to each other; and (b) a special region, wherein the special region has at least one of a source region which is arranged beyond the boundary line and connected to a power source for applying a predetermined potential on the semiconductor substrate, and an empty space region arranged near the boundary line, in which when an adjacent cell has a source region beyond the boundary line, the source region of the adjacent cell can be mounted.
According to the feature of the present invention, a source pattern region (a source diffusion layer and a contact above it) is shared between cells adjacent to each other. Thus, a cell row can be reduced in an upper and lower direction and in a left and right direction. Even if there is no shared source pattern region, it is allowable to arrange any one source pattern region of the cells adjacent to each other while it bestrides between the cells adjacent to each other. Even this case enables the reduction in the cell row. Such a reduction in the cell row enables the reduction in an effective size of a cell, the reduction in a chip size and an improvement of an integration density.
According to the feature of the present invention, a contact pattern region (a substrate contact pattern region) for applying a potential to a semiconductor substrate or a well may be arranged such that it overlaps with a source region formed beyond a cell boundary line. In this case, the cell row can be further reduced.
Other and further objects and features of the present invention will become obvious upon an understanding of the illustrative embodiments about to be described in connection with the accompanying drawings or will be indicated in the appended claims, and various advantages not referred to herein will occur to one skilled in the art upon employing of the invention in practice.